The invention relates to an integrated memory circuit arrangement containing a multiplicity of memory cells arranged in matrix-type fashion in rows and columns. Each memory cell contains at least one memory element. Moreover, a plurality of bit lines in each case lead to the memory cells of the same row. Drive circuits which in each case contain a plurality of drive transistors are arranged on the word lines.
The memory element is e.g., a floating gate transistor, a magnetoresistive memory element, a ferroelectric memory element, a memory element which stores the memory information as a phase (e.g., amorphous or crystalline), or some other memory element.
The drive circuits often contain components whose minimum dimensions are greater than the minimum feature size in the integrated memory circuit arrangement, in particular in comparison with the minimum feature size in the memory cell array. This is attributable e.g., to the fact that higher voltages have to be switched in the drive circuit. Particularly in memory cells which effect nonvolatile storage, drive voltages are required which often amount to a multiple of the operating voltage applied externally to the integrated circuit.
For these and other reasons, there is a need for the present invention.